1. Technical Field of the Invention
The present invention relates to semiconductor device production methods, especially production methods for semiconductor devices having field-shield isolation structures.
2. Background Art
For semiconductor devices which use silicon as semiconductor substrates, LOCOS (Local Oxidation of Silicon) methods have conventionally been used as isolation methods for selectively forming thick thermal oxidation films on the substrates. However, with the LOCOS method, the oxide film regions which grow horizontally from the periphery of the thick thermal oxide film to the active region form obstacles to scaling down known as bird's beaks, so that attention has recently been turned to other techniques, such as field-shield isolation methods.
The field-shield isolation method is a method wherein a MOS structure (hereinafter referred to as a field-shield isolation structure) composed of a field-shield insulation film and a field-shield electrode is provided between the active regions forming the semiconductor element and the field-shield electrode is held at a standard electrical potential (for example, GND or 0 V), whereby parasitic channels are prevented from being formed in the substrate surface in order to isolate the active regions.
An example of a production method for semiconductor devices having field-shield isolation structures is disclosed in Japanese Patent Application, First Publication No. 2-211651. The production method described in this publication shall be explained below as a reference. FIG. 3 is a plan view showing a DRAM memory cell having a field-shield isolation structure, and FIGS. 4A.about.4L are process flow diagrams showing the DRAM memory cell production steps in order.
First, as shown in FIG. 4A, a silicon oxide film 2, a phosphorus-doped polycrystalline silicon film 3 and a silicon oxide film 4 are sequentially formed on the surface of a wafer W formed from a P-type silicon substrate 1. Next, as shown in FIG. 4B, the three films 2, 3 and 4 are patterned into a designated shape so as to form a field-shield gate oxide film 5, a field-shield gate electrode 6 and a field-shield gate cap insulation film 7.
Then, as shown in FIG. 4C, a silicon oxide film 8 is formed on the entire surface of the wafer W, after which side wall spacers 9 are formed by anisotropic etching as shown in FIG. 4D. Next, as shown in FIG. 4E, a silicon oxide film 10 is formed on the surface of the p-type silicon substrate 1, after which a phosphorus-doped polycrystalline silicon film 11 and silicon oxide film 12 are sequentially formed on the entire surface of the wafer W.
Thereafter, as shown in FIG. 4F, a gate oxide film 13, a gate electrode 14 and a gate cap insulation film 15 for a MOS transistor are formed by patterning the films 10, 11 and 12 into a designated shape. Next, as shown in FIG. 4G, an ion implantation of phosphorus is conducted while using these parts 13, 14 and 15 as a mask to form an n-type impurity diffusion layer 16, after which a silicon oxide film 17 is formed over the entire surface of the wafer W as shown in FIG. 4H.
Subsequently, as shown in FIG. 4I, side wall spacers 18 are formed at the side walls of the gate electrode 14 of the MOS transistor by anisotropic etching. Then, as shown in FIG. 4J, after forming a phosphorus-doped polycrystalline silicon film 19 over the entire surface of the wafer W, the bottom electrode 20 of a capacitor is formed by patterning this into a designated shape.
Then, as shown in FIG. 4K, a dielectric film 21 composed of a silicon nitride film is formed on the bottom electrode 20 of the capacitor, and a phosphorus-doped polycrystalline silicon film 22 is formed on the top surface thereof. This is then patterned into a designated shape to form the top electrode 23 of the capacitor as shown in FIG. 4L. Then, after forming an interlayer insulation film 24, contact holes 25 are opened at designated locations, and a wiring layer 28 is formed. A DRAM memory cell having a field-shield isolation structure is formed through the above-given steps.
In semiconductor devices such as the above-mentioned DRAM memory cell shown in FIG. 3, the active regions 26 which form the MOS-type semiconductor element (a MOS transistor in the above example) are defined to be the regions surrounded by the field-shield gate electrode 6. Additionally, with conventional production methods, the side walls of the field-shield gate electrodes 6 stand perpendicular with respect to the surface of the silicon substrate 1 as shown in FIGS. 4B.about.4L.
However, if these side walls are perpendicular, it is difficult to fabricate the gate electrodes 14 of the MOS transistor which extend from within the active regions 26 to the field-shield gate electrode 6 as shown in FIG. 3. That is, a step is formed on the gate electrodes 14 of the MOS transistor at the side wall portions of the field-shield gate electrode 6. However, these steps must be roughly perpendicular because the side walls of the field-shield gate electrodes 6 are roughly perpendicular, making the gate electrodes 14 of the MOS transistor extremely difficult to etch. Additionally, since etching residues can remain between the gate electrodes 14 (the portions indicated by the thick line and labelled with reference numeral 27 in FIG. 3), short circuits can often occur. While this problem can be somewhat relieved by forming a side wall spacer 9 on the side walls 6 of the field-shield gate electrodes 6, this is not sufficient. Additionally, this problem will get even worse as the active regions get smaller due to higher integration of elements, which could cause reduced yields.
Therefore, two methods have been proposed as means for solving this problem. The first method is described in Japanese Patent Application, First Publication No. 2-161753. With this method, the side walls of the field-shield gate electrodes are given an inclination by isotropically etching a conductive film having a single impurity concentration to form the field-shield gate electrodes. Additionally, the second method is described in Japanese Patent Application, First Publication No. 6-238599. With this method, the side walls of the field-shield gate electrodes are made into gradually tapered shapes by etching under conditions wherein the etching rate changes over time when the conductive film is etched.
However, the two above-mentioned methods also have problems. That is, while the side walls of the field-shield gate electrodes are inclined by means of isotropic etching with the first method, isotropic etching usually results in etched surfaces which are curved into concave shapes, so that the upper portions of the side walls become close to perpendicular and the problem is not fully solved. Additionally, since the etching rate is changed over time by changing the concentration of etchant with respect to a conductive film with a uniform impurity concentration according to the second method, the etchant concentration must be changed for each semiconductor wafer when etching, thus presenting problems such as reduced product throughput and poor etch controllability.